1. Field of the Invention
The present invention relates to a signal selecting circuit.
2. Description of the Prior Art
When a plurality of signals are selectively written in a random access memory (hereinafter referred to as RAM) or are read out therefrom in a known circuit where a plurality of input terminals and a plurality of output terminals are connected to the RAM, it is customary that in case the entire input/output systems are synchronized with one another by common clock pulses, input/output buses are switched per required processing time for the RAM so that a plurality of input/output signals can be processed sequentially. However, if the individual input/output systems are in operation nonsynchronously, a longer processing time is required as compared with the synchronous operation. Therefore a block, which corresponds to several-fold writing or reading time, is alloted to each of the input/output systems, and the input/output buses are switched in response to sequential change of the blocks. According to such method, it is impossible to permit simultaneous existence of the input/output signals in the plurality of systems unless a buffer memory is provided for each of the systems.
In the simultaneous operation of merely two systems, the input/output signals can be processed in priority and standby modes without using any buffer memory by processing with priority a first-received command in the two systems. However, in the case of three or more systems, it becomes difficult to achieve satisfactory processing when input/output commands for different systems are received exactly at the same time.
When the nonsynchronized input/output systems are to be processed with a single RAM as mentioned above, it is ordinary in the prior art to solve the problem by using the individual systems in completely different periods of time or by providing a buffer memory of a certain capacity for each of the systems and executing simultaneous input/output operation with respect to the RAM. But the time required for such input/output operation is rendered extremely long, and there arises the problem of requiring separate memories and so forth.